8: Conclusions

latched before the output signals in the bundle are stable. The algorithm used to detect delay faults in the processing logic of the ASC is similar to that exploited in delay testing of combinational circuits [15]. Basically, the pair of test patterns < , > must be applied to the inputs of the combinational circuit to detect its delay path fault. The pair < , > is made up of < @ , @ >, where and are the test vectors applied to the inputs PI of the combinational circuit; and are the state vectors initially loaded into the state registers (Reg1 and Reg2 respectively); the symbol @ denotes the concatenation of bit vectors. In test mode, the test pattern is supplied to the inputs PI and a request signal is generated on the input Rin. The combinational circuit is settled. After receiving an acknowledge event on the input Aout the test is copied into Reg1. The test vector is applied to the inputs PI of the ASC. The test control signal Tst is set to zero and a new request event is generated on the input Rin. As a result, a data path of the combinational block is activated. If there is a delay fault in this path it will cause a delayed response by the combinational circuit whereas the responses are latched after a fixed time determined by the corresponding delay. The scan test technique presented in this paper supports testing for stuck-at and delay faults in ASCs built using the micropipeline design approach. The internal inputs and outputs of the combinational logic block are fully control-lable and observable through the scan path. The test patterns are scanned into the state registers and the test results are shifted out from the register latches, united into one shift register. The test complexity of such a testable ASC is reduced to that of the combinational block. The scan path of the testable ASC is controlled by the STCL block which generates clock signals. The unique structure of the STCL block allows it to be adapted for arranging either a global asynchronous shifting of the test data between different parts of the chip or a local scan path within a particular block. The overall overhead can be estimated only for a particular case since it depends on the complexity of the combinational circuit.